QUery in transition delay after clock tree synthesis

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nathanpk

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Query in transition delay after clock tree synthesis

Hi,

I am new to physical IC design and I am working on CTS now. After CTS when I checked the clock transition time, it seems that rise transition time is different from fall transition time. Can anyone tell me why its different?

Thanks!
 

Rise and fall time of any cell is not same. that the reason we develop clock cells separately which gives almost same rise and fall time
 

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