sun_ray
Advanced Member level 3
I have some question for ASIC synthesis
1. Is it necessary to provide input delay to an input pin of the design on top of setting a driving cell to that particular input pin?
2. Is it necessary to provide output delay to an output pin of the design on top of setting a load (set_load) to that particular output pin?
Please provide explanations also.
1. Is it necessary to provide input delay to an input pin of the design on top of setting a driving cell to that particular input pin?
2. Is it necessary to provide output delay to an output pin of the design on top of setting a load (set_load) to that particular output pin?
Please provide explanations also.