queries for synthesis

[sun_ray]

I have some question for ASIC synthesis

1. Is it necessary to provide input delay to an input pin of the design on top of setting a driving cell to that particular input pin?

2. Is it necessary to provide output delay to an output pin of the design on top of setting a load (set_load) to that particular output pin?


Please provide explanations also.

 

[yx.yang]

To understand this, you need figure out how delay is calcuated at synthesis. What are the delay calcualtion inputs and what are the calculation outputs?
Then, you need understand what does "set_input_delay"/"set_output_delay" used for.
You can get these info from synopsys DC document.

 

[sun_ray]

yx.yang

I read Synopsys DC document long back. Those document I do not have access any more. Please answer my questions precisely if possibe so that I get the to the point answers of my questions.

Thanks for the reply.

REGARDS

 

[yx.yang]

Ok, to my understanding:
1): For input: you need set both input delay and input transition.
2): For output: you need set both output delay and output load.
It's at your choice whether to find out why need set these.

 

[sam536]

Is it necessary to provide input delay to an input pin of the design on top of setting a driving cell to that particular input pin?

<SaM>: Driving cell will give only to make sure, cell is driving by the input port to have an effect in real scenerio. To optimize the better from Input port to register driving input port , Input delay is required. The input delay is to make sure the external delay for the circuit.

2. Is it necessary to provide output delay to an output pin of the design on top of setting a load (set_load) to that particular output pin?

<Sam> : Same answer above will suffice for this. Both are required to have good optimization at synthesis level.

 

[sun_ray]

Is it necessary to provide input delay to an input pin of the design on top of setting a driving cell to that particular input pin?

<SaM>: Driving cell will give only to make sure, cell is driving by the input port to have an effect in real scenerio. To optimize the better from Input port to register driving input port , Input delay is required. The input delay is to make sure the external delay for the circuit.

2. Is it necessary to provide output delay to an output pin of the design on top of setting a load (set_load) to that particular output pin?

<Sam> : Same answer above will suffice for this. Both are required to have good optimization at synthesis level.

Sam

1. But setting driving cell at the input itself will provide the required delay at that particular input for the design under synthesis to model the input. So an input delay may be an additional delay that is being provided in that case. IS not it? Same logic applies to set_load at output and the output delay.

 

[sam536]

Ok. Agree with you. I want to apply 5ns Input delay. How do I put driving cell for that input?. Can you model this wrto existing driving cell?.

Regards, Sam

 

[sun_ray]

Ok. Agree with you. I want to apply 5ns Input delay. How do I put driving cell for that input?. Can you model this wrto existing driving cell?.

Regards, Sam

In that case, I will only put a set_input delay for 5 ns and will not set any driving cell for that particular input. So in this case I will use only input_delay and not driving cell on top of setting input delay of 5 ns. Please correct me if I am wrong.

Regards

 

[yx.yang]

In that case, I will only put a set_input delay for 5 ns and will not set any driving cell for that particular input. So in this case I will use only input_delay and not driving cell on top of setting input delay of 5 ns. Please correct me if I am wrong.

Regards

To correct calculate the delay of the first cell the input pin drive, just set input delay is not enough.
1): For input: you need set both input delay and input transition.
2): For output: you need set both output delay and output load.

For why, you need figure out how delay is calcuated by current synthesis tools. What are the delay calcualtion inputs and what are the delay calculation outputs?

 

[sun_ray]

To correct calculate the delay of the first cell the input pin drive, just set input delay is not enough.
1): For input: you need set both input delay and input transition.
2): For output: you need set both output delay and output load.

For why, you need figure out how delay is calcuated by current synthesis tools. What are the delay calcualtion inputs and what are the delay calculation outputs?

Yang

Good point. It helps to understand the topic.

To calculate the delay of the first cell the input pin drive, the tool will need the input transition time at that particular input. So if we set an input delay of 5 ns, the tool can calculate how much will be the transition time at that input if the input delay is 5 ns and thus calculate the delay of the first cell the input pin drive. In that case we do not need driving cell at the input.

Regards