this is my test bench code, i used modelsim tool that automatically generates the test bench. i added the clocks and the input results
LIBRARY ieee ;
LIBRARY lpm ;
USE ieee.std_logic_1164.all ;
USE lpm.all ;
ENTITY divide_int_tb2 IS
END ;
ARCHITECTURE divide_int_tb2_arch OF divide_int_tb2 IS
SIGNAL remain : std_logic_vector (31 downto 0) ;
SIGNAL clock : STD_LOGIC:='0';
SIGNAL quotient : std_logic_vector (31 downto 0) ;
SIGNAL numer : std_logic_vector (31 downto 0) ;
SIGNAL denom : std_logic_vector (31 downto 0) ;
COMPONENT divide_int
PORT (
remain : out std_logic_vector (31 downto 0) ;
clock : in STD_LOGIC ;
quotient : out std_logic_vector (31 downto 0) ;
numer : in std_logic_vector (31 downto 0) ;
denom : in std_logic_vector (31 downto 0) );
END COMPONENT ;
BEGIN
clock <= not(clock) after 5 ns;
DUT : divide_int
PORT MAP (
remain => open ,
clock => clock ,
quotient => quotient ,
numer => numer ,
denom => denom ) ;
verify: process
begin
numer<= x"41500000"; --13
denom<= x"40A00000"; --5
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
end process;
END ;
- - - Updated - - -
here is the LPM_divide code
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY LPM_divide_inst IS
PORT
(
clock : IN STD_LOGIC ;
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END LPM_divide_inst;
ARCHITECTURE SYN OF lpm_divide_inst IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
remain <= sub_wire0(31 DOWNTO 0);
quotient <= sub_wire1(31 DOWNTO 0);
LPM_DIVIDE_component : LPM_DIVIDE
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_pipeline => 5,
lpm_type => "LPM_DIVIDE",
lpm_widthd => 32,
lpm_widthn => 32
)
PORT MAP (
clock => clock,
denom => denom,
numer => numer,
remain => sub_wire0,
quotient => sub_wire1
);