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Quartus Megafunction tool LPM_divide

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noora_vhdl

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Hi,
i am using the megafunction tool LPM_divide to do integer divide. when i run the test bench for the code i don't get the desired results, and the quotient is always x"00000001".

is this because the device i am using is cyclone and not stratix. in the documentation provided with the divide function it only mentions stratix, does this mean the function only supports stratix?
 

FvM

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LPM_divide is generating a parallel divider with logic elements and works for all Altera devices, provided you have enough logic cells available. You are apparently doing something wrong.
 

TrickyDicky

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have you got enough bits in the numerator and denominator?

remember that 5/3 = 1 remainder 2
adding more bits to the numerator in effect adds more fractional bits to the quotient.
 

noora_vhdl

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LPM_divide is generating a parallel divider with logic elements and works for all Altera devices, provided you have enough logic cells available. You are apparently doing something wrong.

i know it should be a very simple process, but i cant seem to understand where is the porblem. Do you think the problem is in the test bench that i have generated?
 

TrickyDicky

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i know it should be a very simple process, but i cant seem to understand where is the porblem. Do you think the problem is in the test bench that i have generated?

Yes, post some code.
 

noora_vhdl

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have you got enough bits in the numerator and denominator?

remember that 5/3 = 1 remainder 2
adding more bits to the numerator in effect adds more fractional bits to the quotient.

all my inputs and outputs are 32 bits.

i am getting wrong results on both my of my output ports. i tried several different inputs, for some reason the output is always x"00000001", the remainder value changes but it still gives incorrect results
 

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Why don't you show the code, including LPM_divide parameters?
 

noora_vhdl

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this is my test bench code, i used modelsim tool that automatically generates the test bench. i added the clocks and the input results

LIBRARY ieee ;
LIBRARY lpm ;
USE ieee.std_logic_1164.all ;
USE lpm.all ;
ENTITY divide_int_tb2 IS
END ;

ARCHITECTURE divide_int_tb2_arch OF divide_int_tb2 IS
SIGNAL remain : std_logic_vector (31 downto 0) ;
SIGNAL clock : STD_LOGIC:='0';
SIGNAL quotient : std_logic_vector (31 downto 0) ;
SIGNAL numer : std_logic_vector (31 downto 0) ;
SIGNAL denom : std_logic_vector (31 downto 0) ;
COMPONENT divide_int
PORT (
remain : out std_logic_vector (31 downto 0) ;
clock : in STD_LOGIC ;
quotient : out std_logic_vector (31 downto 0) ;
numer : in std_logic_vector (31 downto 0) ;
denom : in std_logic_vector (31 downto 0) );
END COMPONENT ;
BEGIN
clock <= not(clock) after 5 ns;
DUT : divide_int
PORT MAP (
remain => open ,
clock => clock ,
quotient => quotient ,
numer => numer ,
denom => denom ) ;
verify: process
begin
numer<= x"41500000"; --13
denom<= x"40A00000"; --5
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
wait until (clock' event and clock= '1');
end process;

END ;

- - - Updated - - -

here is the LPM_divide code


LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY LPM_divide_inst IS
PORT
(
clock : IN STD_LOGIC ;
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END LPM_divide_inst;


ARCHITECTURE SYN OF lpm_divide_inst IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);



COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
remain : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
denom : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;

BEGIN
remain <= sub_wire0(31 DOWNTO 0);
quotient <= sub_wire1(31 DOWNTO 0);

LPM_DIVIDE_component : LPM_DIVIDE
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_pipeline => 5,
lpm_type => "LPM_DIVIDE",
lpm_widthd => 32,
lpm_widthn => 32
)
PORT MAP (
clock => clock,
denom => denom,
numer => numer,
remain => sub_wire0,
quotient => sub_wire1
);
 

TrickyDicky

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x"41500000" is not 13
x"40A00000" is not 5

x"41500000" / x"40A00000" = x"00000001" remainder x"00B00000"

What numbers are you trying to divide?

13 in hex = x"0000000C"
5 = x"00000005"

= x"00000002" remainder x"00000003"

So there is nothing wrong with the code - there is something wrong with your expectation.
 

noora_vhdl

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but i am using this online calculator that converts numbers from decimal to hex and the other way round

here have a look
IEEE-754 Analyser-.gif

also here is the link https://babbage.cs.qc.cuny.edu/IEEE-754/
 

FvM

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Apparently 32 bit single precision float format. LPM_DIVIDE expects signed or unsigned integer.
 

noora_vhdl

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yes i know. but what does that mean? what am i doing wrong?
 

TrickyDicky

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an integer is an integer. so each bit represents 2^n (where n is the position)
floating point is a different format, where bit 32 is the sign bit, the next 12 bits are the mantissa, and the next 23 bits are the power to raise the mantissa by. So the formatting is completly different.

So forget that float calculator. All you need is an integer.
 

noora_vhdl

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ok!!
thank you soo much for your help

- - - Updated - - -

ok!!
thank you soo much for your help
 

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