QPSK demodulation .. Help reqd urgently!!

[aleenathomas]

Hi..
Im trying to implement QPSK modulator and demodulator in FPGA using verilog. In the QPSK demod, first I multiply the QPSK signal with Sine values(Q channel) and Cosine values (I channel) stored in Look Up Table, then give it to integrator where summation with previous inputs are done. Then the sign bit of the values(Decision block) are considered, and are given to a Multiplexer where serial to parallel conversion is being done.

The problem is that the demodulated signal is not matching the modulation signal. Is it necessary to put some threshold values on the output of the Decision block other than considering the Sign bit. I have cross verified the codes I had given, but couldn't sort out the issue. Any help would be much appreciated. As the project submission date is nearing, I'm much worried..
thanks in advance
Aleena:|

 

[Mina Magdy]

is the problem in your design or in the code you write (i mean are you sure from your design )

 

[aleenathomas]

Hi Mina..
thank you for your reply.. i have used the same block diagram given.. in the matched filter i have multiplied the modulated signal with sine and Cosine values.. then given an integrator (which adds the input with the previous input given to it).. decision device I used the sign bit of the integrator output.. then combined multiplexed the two.. i believe the problem may be related with the threshold value to be chosen at the decision device.. I sought help from project training center, but they couldn't help me either.. if you have any demodulator verilog code which will work kindly share.. suggestions needed..:-(

 

[Mina Magdy]

i think the problem may be in the low pass filter this is a low pass filter

https://www.edaboard.com/threads/19844/

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[permute]

do you have carrier/baud lock? is the QPSK constellation correctly aligned at the receiver and not rotating.

Likewise, is the system spectrally inverted? eg, are you swapping cos/sin, or multiplying by the wrong sign for cos/sin on one phase, or etc...