samiran_dam
Full Member level 2
Dear All,
I have to design a Push-Pull Source Follower Output Stage with 1.8 V - to -0 V supply rail. The input to this stage is from a two-stage differential amplifier's output. I have few question regarding this:
1. How should I initially DC bias the push and pull transistors? Does these transistors need to be in saturation region when there is no input signal?
2. As the dc operating point keeps on changing for the push-pull transistors with the variation of the output signal, the output impedance also changes. So, what will be the measure of output impedance?
3. What circuit should I use for avoiding cross-over distortion? I opted for the topology shown below (ref.: CMOS Analog Circuit Design - Allen & Holberg):
In this circuit transistor M8 and M9 are used to provide a level shift (M8 shifts up for the push transistor , M12 and M9 shifts down for the pull transistor, M13) for avoiding the cross-over distortion arising class-B operation. In this circuit, is not the advantage we are supposed to get in terms of rail-to-rail output swing (due to push-pull action) suppressed by the fact that the swing of the signal driving the gate of M13 are limited by the saturation constraint of the current sink transistor, M10 of the shifter stage? I mean we should keep the M10 transistor always in saturation, right? [similar argument for M7 too].
4. Class-AB (as shown in the figure) push-pull stage is used mainly to reduce the quiescent power consumption (and hence increasing the efficiency). This means in the overlapping region of sourcing and sinking operation of respectively push and pull transistors, minimal amount of quiescent current should flow. Keeping this in mind, I have to DC bias the output stage, right?
Please help me by clarifying my doubts as far as possible.
Regards,
Sam
P.S.: One more topology to avoid the crossover distortion is suggested in literature as shown [ref text book: Operational Amplifiers - by Huijsing]:
Is this circuit more robust than the one shown above?
I have to design a Push-Pull Source Follower Output Stage with 1.8 V - to -0 V supply rail. The input to this stage is from a two-stage differential amplifier's output. I have few question regarding this:
1. How should I initially DC bias the push and pull transistors? Does these transistors need to be in saturation region when there is no input signal?
2. As the dc operating point keeps on changing for the push-pull transistors with the variation of the output signal, the output impedance also changes. So, what will be the measure of output impedance?
3. What circuit should I use for avoiding cross-over distortion? I opted for the topology shown below (ref.: CMOS Analog Circuit Design - Allen & Holberg):
In this circuit transistor M8 and M9 are used to provide a level shift (M8 shifts up for the push transistor , M12 and M9 shifts down for the pull transistor, M13) for avoiding the cross-over distortion arising class-B operation. In this circuit, is not the advantage we are supposed to get in terms of rail-to-rail output swing (due to push-pull action) suppressed by the fact that the swing of the signal driving the gate of M13 are limited by the saturation constraint of the current sink transistor, M10 of the shifter stage? I mean we should keep the M10 transistor always in saturation, right? [similar argument for M7 too].
4. Class-AB (as shown in the figure) push-pull stage is used mainly to reduce the quiescent power consumption (and hence increasing the efficiency). This means in the overlapping region of sourcing and sinking operation of respectively push and pull transistors, minimal amount of quiescent current should flow. Keeping this in mind, I have to DC bias the output stage, right?
Please help me by clarifying my doubts as far as possible.
Regards,
Sam
P.S.: One more topology to avoid the crossover distortion is suggested in literature as shown [ref text book: Operational Amplifiers - by Huijsing]:
Is this circuit more robust than the one shown above?
