Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

purpose of analog mix signal simulations?

Status
Not open for further replies.

ashishk

Junior Member level 2
Joined
Dec 29, 2010
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,419
Hi,

Can anyone please tell me what is real purpose of doing analog mix signal simulation with digital and analog netlists? When we already do digital functional verification with analog behavioral models and spice simulations for analog separately then why do we need to do AMS. Is it something we will achieve there? How is this different from subsystem level to SOC level?

Thanks,
Ashish
 

ljxpjpjljx

Advanced Member level 3
Joined
May 5, 2008
Messages
972
Helped
80
Reputation
162
Reaction score
55
Trophy points
1,308
Location
Shang Hai
Activity points
4,679
AMS is more accurate while incisive simulator not so good for mix-signal simulation !
 

ashishk

Junior Member level 2
Joined
Dec 29, 2010
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,419
But why do we have it at first place. Cant we verify digital block and analog block separately. Is the purpose of this is to check connectivity? I dont believe this.There got to be something else that we are achieving but I don't know that. Can you please explain.

Thanks,
Ashish
 

GI

Member level 2
Joined
Nov 10, 2008
Messages
48
Helped
31
Reputation
62
Reaction score
31
Trophy points
1,298
Location
Istanbul/Turkiye
Activity points
1,721
Hi Ashish,

I'm not an AMS expert, but I guess the reason may be similar to block level budgeting done at top level:

For example, in backend implementation most of the time a top level is partitioned into blocks in order to cope with complexity. During partitioning, timings at inputs & outputs of the block are budgeted as a rough estimation. However after implementation of blocks finalized, and you try to plug them at top level one can encounter timing problems, which were impossible to see at block level (better budgeting means less deviation from this). Making an analogy with this, one of the reasons maybe to verify co-habitation of analog & digital blocks in addition to running simulations with "behavioral" models, and see whether the circuit behaves exactly it is designed for. Otherwise you'll never know if there is any issue at the analog-digital interface, as behavioral models are perfect models not including any timing/transition information which are very important especially after circuit layout is done.

As I said previously, I'm not a mixed signal expert, so my answer is based on an analogy. Hope it helps.

BR,
Gokhan
---
 
Last edited:

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top