Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Pulse Peak Track Hold And Reste circuit

Status
Not open for further replies.

trastikata

Member level 1
Joined
Apr 28, 2007
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,631
Pulse Peak Track Hold And Reset circuit

Hello,

I want to measure the peak value of short pulses (close to Gaussian form and about 0.5 - 1 usec duration) spaced at least 50 - 100 usec from each other.

I came up with the attached circuit where the first amplifier tracks the peak value and the second buffers the voltage. The comparator provides the track, hold for the duration of the rising and falling edge, and reset timing 5 usec after the falling edge goes to zero.

The MCU will trigger on the falling edge of the pulse and ADC needs about 2 usec to measure the value of the peak, which is provided by the comparator and then the peak is reset again by the comparator.

The simulation works in terms of functionality, obviously the OPAMPs will be different and chosen accordingly. But I don't have much experience in the analog part and I would like to ask for advises and suggestion if and how to improve my schematic.

EDIT:
The title should read "Reset" instead of "Reste" :smile:
 

Attachments

  • PPTAH.png
    PPTAH.png
    358.3 KB · Views: 149
Last edited:

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
23,045
Helped
4,716
Reputation
9,448
Reaction score
5,092
Trophy points
1,393
Activity points
152,662
Hi,

There is no question.
Please elaborate a clear, detailed question.

****
Generally I recommedn that you do what all the professinals need to to, too: Redaing the datasheet.
Especially the tables:
Example:
1) Absolute maximum ratings and operation conditions:
* VCC: 14V ---> you are wihtin the specified range
* Vid. +/-1V ---> I assume you are not within the specified range. Check with your simulation.
do this item by item.

Klaus
 

trastikata

Member level 1
Joined
Apr 28, 2007
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,631
Thank you for your suggestions Klaus.

My question is - is there a principal error in the analogue design that I miss and could cause problems?
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
23,045
Helped
4,716
Reputation
9,448
Reaction score
5,092
Trophy points
1,393
Activity points
152,662
Hi,

The Vid may be an error. You have to check.

There may be some issues a simulator possibly doesn´t show:
* driving a 10nF capacitance is not easy, some OPAMPs may have problems with this. Why that big capacitor?
* when input_voltage < Capacitor_voltage, then the OPAMP goes into saturation. Input stage as well as output stage. This may cause a lot of "delay" time for the OPAMP to get back into clean "regulated" state. But with single supply a clean solution is difficult.
* the comparator already has openCollector/openDrain output. I wonder why there are another two openDrain stages in series with it.
* from your diagram you see that you have to ensure at least 35us of very low input voltage before the next pulse, else the capacitor does not become discharged.

Klaus
 

trastikata

Member level 1
Joined
Apr 28, 2007
Messages
36
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,631
Thank you, much appreciate your feedback and help!

- lowered the input capacitor value as you suggested.
- missed the fact that the comparator is an open drain - I eliminated the FET switches.
- did not have an appropriate OPAMP model for simulation, thus I used this. The actual OPAMP will be different and within specifications.
- time between the pulses will be at least 50 to 100 usec - this should be sufficient time for the cap to discharge.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top