I have a general question regarding the PSR of the LDO. What type of pass element (NMOS or PMOS) gives better PSR if all the other circuit elements are the same?
We could say we have a high impedance between output and ground in PMOS pass element case which couples a large portion of supply noise in contrast to common drain which has a low output impedance in NMOS pass element case?
The problem with the PMOS (and PNP) pass element
is that its Miller capacitance tends to magnify supply
perturbations with close-in high (and variable) gain,
and the error amplifier has to defeat this (but cannot,
at higher frequencies, if it is designed with limited
power and slew rate).
Especially where lazy designers have chosen to make
the PMOS pass device "forward pole" the main
compensation capacitor, neglecting that it also adds
a "supply zero".
The problem with the PMOS (and PNP) pass element
is that its Miller capacitance tends to magnify supply
perturbations with close-in high (and variable) gain,
and the error amplifier has to defeat this (but cannot,
at higher frequencies, if it is designed with limited
power and slew rate).
Especially where lazy designers have chosen to make
the PMOS pass device "forward pole" the main
compensation capacitor, neglecting that it also adds
a "supply zero".
The PMOS pass FET when driven by the gate, will
feed back an amplified negative image via Cdg.
That's your "forward pole". Capacitive negative
feedback.
The same FET driven by the source (as in power
supply, and its rejection) has a positive gain to VOUT.
When VIN rises and VOUT is static(-ish) then |Vds|
increases (Vds negative-going). Vgs will be moved
to follow Vds, by Cdg. So the FET will turn on more.
You have to look at things "upside down" compared
to how most people think of the parasitics and
drive / action based on a NMOS paradigm.