Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PSR of LDO based on pass element type

deep_sea

Full Member level 1
Joined
Oct 23, 2019
Messages
98
Helped
14
Reputation
28
Reaction score
16
Trophy points
8
Activity points
791
I have a general question regarding the PSR of the LDO. What type of pass element (NMOS or PMOS) gives better PSR if all the other circuit elements are the same?
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,418
Helped
2,154
Reputation
4,313
Reaction score
2,028
Trophy points
1,393
Location
USA
Activity points
59,388
The problem with the PMOS (and PNP) pass element
is that its Miller capacitance tends to magnify supply
perturbations with close-in high (and variable) gain,
and the error amplifier has to defeat this (but cannot,
at higher frequencies, if it is designed with limited
power and slew rate).

Especially where lazy designers have chosen to make
the PMOS pass device "forward pole" the main
compensation capacitor, neglecting that it also adds
a "supply zero".
 

deep_sea

Full Member level 1
Joined
Oct 23, 2019
Messages
98
Helped
14
Reputation
28
Reaction score
16
Trophy points
8
Activity points
791
The problem with the PMOS (and PNP) pass element
is that its Miller capacitance tends to magnify supply
perturbations with close-in high (and variable) gain,
and the error amplifier has to defeat this (but cannot,
at higher frequencies, if it is designed with limited
power and slew rate).

Especially where lazy designers have chosen to make
the PMOS pass device "forward pole" the main
compensation capacitor, neglecting that it also adds
a "supply zero".
Could you please elaborate why it has a supply zero? which RC case this zero?
What is meant by forward pole?
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
7,418
Helped
2,154
Reputation
4,313
Reaction score
2,028
Trophy points
1,393
Location
USA
Activity points
59,388
The PMOS pass FET when driven by the gate, will
feed back an amplified negative image via Cdg.
That's your "forward pole". Capacitive negative
feedback.

The same FET driven by the source (as in power
supply, and its rejection) has a positive gain to VOUT.
When VIN rises and VOUT is static(-ish) then |Vds|
increases (Vds negative-going). Vgs will be moved
to follow Vds, by Cdg. So the FET will turn on more.

You have to look at things "upside down" compared
to how most people think of the parasitics and
drive / action based on a NMOS paradigm.
 

LaTeX Commands Quick-Menu:

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top