willzz
Newbie level 3
Hi all,
I am trying to prototype a design into FPGA(Altera). Right now I am having difficulties closing setup timing. critical timing path seem to have very long net routing delay.
The way to fix in ASIC is to break the long net into sections and insert buffers if needed, or simply upsize the driver strength.
I am using the quartus prime v16 lite version for the implemention. and I dont have a lot of FPGA experience.
Can someone please give me some ideas? to implement something similar to what i mentioned above? or provide alternative solutions ?
Thanks!!
I am trying to prototype a design into FPGA(Altera). Right now I am having difficulties closing setup timing. critical timing path seem to have very long net routing delay.
The way to fix in ASIC is to break the long net into sections and insert buffers if needed, or simply upsize the driver strength.
I am using the quartus prime v16 lite version for the implemention. and I dont have a lot of FPGA experience.
Can someone please give me some ideas? to implement something similar to what i mentioned above? or provide alternative solutions ?
Thanks!!