Programmable Duty Cycle Clk Signal

[Edward_2288]

Hi,

I want to design a programmable duty cycle clock signal, based on 32kHz reference clock. the programmable duty cycle clock signal ha
s frequency of 1kHz. the duty cycle can vary in term of 5%, i.e. 5%, 10% ... 95%.

so anyone has the idea with minimum hardware constraint.
thanks.if possible, can you show the verilog code for this module.

 

[eda_wiz]

a free PWM core is available here.
**broken link removed**

 

[Edward_2288]

is there any simplified version of the verilog code? I cant really understand it. thx

 

[JesseKing]

seemed easy,
but your reference clk is not appropriate

 

[skyismylimit]

The master clock u are chooosing must be high enough to generate all the possible duty cycle...

think some counter logic would solve the job...