There looks to be a lot of glitching in the logic outputs
and my first guess would be that you are overclocking
the layers of decision logic and catching an unsettled
comparator output, or something like that. If this is a
pipeline with multiple layers of add & carry, that might
add up to more than 30nS setup time if you add in the
analog portions of the chain.
I would go backward from whatever logic is responsible
for the gang-flipped bits, looking for timing binds.