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problem with the output of ADC when sampling rate is high

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kickbeer

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Hi,

I have just discovered something strange with my 8-bit Folding and Interpolating ADC when the sampling rate is higher than 30 MHz. As you can see in attachment, when the input signal (V(vin)) 0 V (just ignore 1 V because it is the DC offset) the output of my ADC showed '00111111'. It must be '00000000'. Does anyone experience this kind of problem before? How to solve this?
 

dick_freebird

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There looks to be a lot of glitching in the logic outputs
and my first guess would be that you are overclocking
the layers of decision logic and catching an unsettled
comparator output, or something like that. If this is a
pipeline with multiple layers of add & carry, that might
add up to more than 30nS setup time if you add in the
analog portions of the chain.

I would go backward from whatever logic is responsible
for the gang-flipped bits, looking for timing binds.
 

    kickbeer

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JoannesPaulus

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It seems to me that you are looking at one sample too early. At about 280ns you have all zeros. Are you accounting for a pipeline delay?
 

kickbeer

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Re: problem with the output of ADC when sampling rate is hig

dick_freebird said:
There looks to be a lot of glitching in the logic outputs
and my first guess would be that you are overclocking
the layers of decision logic and catching an unsettled
comparator output, or something like that. If this is a
pipeline with multiple layers of add & carry, that might
add up to more than 30nS setup time if you add in the
analog portions of the chain.

I would go backward from whatever logic is responsible
for the gang-flipped bits, looking for timing binds.
What did you mean by overclocking actually? Ton of my clock is 3.3 V and it is just connected to my comparator. I think is ok because less than 3.3 will make my comparator does not work properly.My digital parts are not clocked actually.

Added after 21 minutes:

JoannesPaulus said:
It seems to me that you are looking at one sample too early. At about 280ns you have all zeros. Are you accounting for a pipeline delay?
all zeros are actually what i want. after the bit '00001' the digital output of fine quantizer jump to '11111' instead of '00000' which i wish should be. After '11111' it finally it jumps to '00000'. These result are quite strange. In the attachment you can see the xor encoder which encode my 32 comparator outputs into 5-bit binary output. Any comment would be very appreciated
 

JoannesPaulus

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You should definitely clock your digital!
What is the delay of one XOR gate? You have 5 of them in series. Is 5*td(XOR)<Tclk?
 

    kickbeer

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kickbeer

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Re: problem with the output of ADC when sampling rate is hig

JoannesPaulus said:
You should definitely clock your digital!
What is the delay of one XOR gate? You have 5 of them in series. Is 5*td(XOR)<Tclk?
Hello Joannes,

According to library in LTSpice, the gates are ideal and the delay of one XOR should be at 0ns. Anyway i tried to simulate according to what you said but i still got the same old result. See my clocking part in the attachment. The speed of the D flip-flop is same with the sped of the clock for comparator.

Regard,
Bruno
 

JoannesPaulus

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So, unless the logic is incorrect the problem is not in your exor encoder...
 

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