Problem with skew in a clock divider code

[Tom2]

I try to used a code for clock divider to used it to an FPGA.I wrote the code and i tested on modelsim and is right.The problem is that on synthesis (xilinx) i have a warning about skew which create problem when i used fpga and fpga do not work ok.
Is anyone who know the problem and what i did wrong on the code?????
The code is pellow:


----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:11:51 10/02/2006
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity divider is
Port ( Clock : in STD_LOGIC;
Clock2 : out STD_LOGIC);
end divider;

architecture Behavioral of divider is

signal counter : STD_LOGIC_Vector(31 downto 0):=(X"00000000");
signal Cout : STD_LOGIC:='0';

begin
Process(Clock,Cout)
Begin
if rising_edge(Clock) then
counter<=counter + 1;
if counter=100000000 then
counter<=(X"00000000");
Cout<=not Cout;
else
Cout<=Cout;
end if;
end if;
Clock2<=Cout;
End process;

end Behavioral;

 

[lordsathish]

Re: clock divider

Hi could you tell what was the warning that you were getting...

I think this code could be better for you... i wont show any warnings i hope...

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY barca IS
-- Declarations
Port ( Clock : in STD_LOGIC;
Clock2 : out STD_LOGIC);

END barca ;

-- hds interface_end
ARCHITECTURE ars OF barca IS
signal counter : STD_LOGIC_Vector(31 downto 0):=(others=>'0');
BEGIN
Process(Clock)
Begin
if rising_edge(Clock) then
counter<=counter +"00000000000000000000000000000001";
if counter="10000000000000000000000000000000" then
counter<=(others=>'0');
end if;
end if;

End process;

Clock2<=counter(31);



END ars;

 

[Iouri]

clock divider

Why do you need second "if" you can do cout <= counter(31);

also general comment when you do reset better will be counter <= (others => '0');


regards

 

[cheggy]

Re: clock divider

counter<=counter+1;

...and it works all alone !