Tom2
Full Member level 5

I try to used a code for clock divider to used it to an FPGA.I wrote the code and i tested on modelsim and is right.The problem is that on synthesis (xilinx) i have a warning about skew which create problem when i used fpga and fpga do not work ok.
Is anyone who know the problem and what i did wrong on the code?????
The code is pellow:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:11:51 10/02/2006
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
Port ( Clock : in STD_LOGIC;
Clock2 : out STD_LOGIC);
end divider;
architecture Behavioral of divider is
signal counter : STD_LOGIC_Vector(31 downto 0):=(X"00000000");
signal Cout : STD_LOGIC:='0';
begin
Process(Clock,Cout)
Begin
if rising_edge(Clock) then
counter<=counter + 1;
if counter=100000000 then
counter<=(X"00000000");
Cout<=not Cout;
else
Cout<=Cout;
end if;
end if;
Clock2<=Cout;
End process;
end Behavioral;
Is anyone who know the problem and what i did wrong on the code?????
The code is pellow:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:11:51 10/02/2006
-- Design Name:
-- Module Name: divider - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divider is
Port ( Clock : in STD_LOGIC;
Clock2 : out STD_LOGIC);
end divider;
architecture Behavioral of divider is
signal counter : STD_LOGIC_Vector(31 downto 0):=(X"00000000");
signal Cout : STD_LOGIC:='0';
begin
Process(Clock,Cout)
Begin
if rising_edge(Clock) then
counter<=counter + 1;
if counter=100000000 then
counter<=(X"00000000");
Cout<=not Cout;
else
Cout<=Cout;
end if;
end if;
Clock2<=Cout;
End process;
end Behavioral;