1) whenebver i initialise the variabe , it gives a warning that its is not initialised and is ignored.
2) does not recognise signal or variables of type TIME
b<=a after 20ns; -- gives an error .. it cannot recognize "n";
3) Can someone explain RTL in a few lines .
apart from the syntax error (missing space with 20 ns) as you referred to RTL: This kind of delay statements are for simulation only, they can't be synthesized to hardware respectively used for register transfer level description.
Hello,
Concerning point (1), variables can only be declared inside a process. It can not be intialized inside an architecture outside the process. If you want to declare something at the architecture level, use signals instead.
as for the variables, they come before the begin keyword of a process statement (so they have to be declared inside a certain process)
P1: process (A)
variable X : .....;
begin
....
end process;
///////////
as for RTL, it means synthesizable code...or code that can be implemented actually with components....the delay statements, for example, aren't synthesizable!
Hi,
1- Variable must be declared and assigned a default value in the package file
2- Space between the time space value and the time unit is missing. (20 ns
3- Read more.
It's a bad exemple of tools. I should said modelsim and NCSim for simulation if you want (since simulable code don't imply that it is synthesisable).
VHDL is a language it's usage depend on the tools.
Suppose you have a synthesisable code. This imply that this code it is simulable. Unfortunately this is not always true is u r using Modelsim for simulation and DC for synthesis.
whenever an event has to be carried out at the network level....
say an addition/subtraction/division or any event....
high level abstractions are used to define the processor architecture...
this is known as register transfer level description...
it describes the operation of a system without reference to specific components....