Problem with initializing variables in VHDL

[smileysam]

1) whenebver i initialise the variabe , it gives a warning that its is not initialised and is ignored.
2) does not recognise signal or variables of type TIME
b<=a after 20ns; -- gives an error .. it cannot recognize "n";
3) Can someone explain RTL in a few lines .

 

[muralicrl]

Re: doubts in vhdl

Hi,

Kindly try like this
b <= a after 20 ns;

Regards,

N.Muralidhara

 

[omara007]

doubts in vhdl

where do you originally declare the variables and signals ?

 

[smileysam]

Re: doubts in vhdl

varibale declaration ..... after architecture and before the begin statement.

 

[FvM]

Re: doubts in vhdl

Hello,

apart from the syntax error (missing space with 20 ns) as you referred to RTL: This kind of delay statements are for simulation only, they can't be synthesized to hardware respectively used for register transfer level description.

Regards,
Frank

 

[ieropsaltic]

Re: doubts in vhdl

Hello,
Concerning point (1), variables can only be declared inside a process. It can not be intialized inside an architecture outside the process. If you want to declare something at the architecture level, use signals instead.

 

[salma ali bakr]

Re: doubts in vhdl

varibale declaration ..... after architecture and before the begin statement.

the signals should only be there...

as for the variables, they come before the begin keyword of a process statement (so they have to be declared inside a certain process)

P1: process (A)

variable X : .....;

begin
....

end process;

///////////

as for RTL, it means synthesizable code...or code that can be implemented actually with components....the delay statements, for example, aren't synthesizable!

 

[master_picengineer]

doubts in vhdl

Hi,
1- Variable must be declared and assigned a default value in the package file
2- Space between the time space value and the time unit is missing. (20 ns
3- Read more.

 

[salma ali bakr]

Re: doubts in vhdl

Hi,
1- Variable must be declared and assigned a default value in the package file

it can also be declared and defined inside a process statement
you don't have to use packages

 

[master_picengineer]

Re: doubts in vhdl

Hi,
1- Variable must be declared and assigned a default value in the package file

it can also be declared and defined inside a process statement
you don't have to use packages

Hi Salma,
Yes you 're right but this depend on the tools used. I agree with you for DC but for modelsim packages are needed.

 

[salma ali bakr]

Re: doubts in vhdl

mmm
i don't get what you mean
it's all VHDL at the end
DC is for synthesis
Modelsim is for simulation
i don't see the relation!!!

 

[master_picengineer]

Re: doubts in vhdl

mmm
i don't get what you mean
it's all VHDL at the end
DC is for synthesis
Modelsim is for simulation
i don't see the relation!!!

It's a bad exemple of tools. I should said modelsim and NCSim for simulation if you want (since simulable code don't imply that it is synthesisable).
VHDL is a language it's usage depend on the tools.
Suppose you have a synthesisable code. This imply that this code it is simulable. Unfortunately this is not always true is u r using Modelsim for simulation and DC for synthesis.

 

[salma ali bakr]

Re: doubts in vhdl

yah...i know that
but VHDL doesn't depend on the tool..it's just a way to describe the circuit...whatever the tool is...

i don't see the link of mentioning packages and their relation with the tools...it's irrelevant! that's just my point correct me if i'm wrong plz

 

[master_picengineer]

doubts in vhdl

You're right. But, my experience with Modelsim 5.7 tough me that variables must be declared with their default value in the package file.

 

[salma ali bakr]

Re: doubts in vhdl

hehe

ok...modelsim can be annoying sometimes

 

[Mejdi_tn]

doubts in vhdl

Hi,
Variable will be declared and assigned in the package file

 

[Kazzam]

Re: doubts in vhdl

whenever an event has to be carried out at the network level....
say an addition/subtraction/division or any event....
high level abstractions are used to define the processor architecture...
this is known as register transfer level description...
it describes the operation of a system without reference to specific components....


regards
kazzam.....