Sep 17, 2007 #1 V vinodkumar Full Member level 5 Joined Oct 5, 2006 Messages 251 Helped 12 Reputation 24 Reaction score 3 Trophy points 1,298 Location hyderabad Activity points 2,822 Hi ,iam unable to get the output signls in the objects,waveform for verilog in qsim,for the simple code written has shown below: module ffpos(clk, d, q); input clk; input d; output q; reg q; always@(posedge clk) begin q<=d; end endmodule IS there any error in the code written,but iam getting evrything well for VHDL.wht could be the reason.
Hi ,iam unable to get the output signls in the objects,waveform for verilog in qsim,for the simple code written has shown below: module ffpos(clk, d, q); input clk; input d; output q; reg q; always@(posedge clk) begin q<=d; end endmodule IS there any error in the code written,but iam getting evrything well for VHDL.wht could be the reason.
Sep 17, 2007 #2 avimit Banned Joined Nov 16, 2005 Messages 412 Helped 91 Reputation 182 Reaction score 23 Trophy points 1,298 Location Fleet, UK Activity points 0 Re: questasim-doubt Hi I can only say there is nothing wrong with the code. Kr, Avi http://www.vlsiip.com
Re: questasim-doubt Hi I can only say there is nothing wrong with the code. Kr, Avi http://www.vlsiip.com
Sep 19, 2007 #3 V vinodkumar Full Member level 5 Joined Oct 5, 2006 Messages 251 Helped 12 Reputation 24 Reaction score 3 Trophy points 1,298 Location hyderabad Activity points 2,822 Re: questasim-doubt hi ,iam able to get rid of this,there is an option of optimize the design a checkbox,which was selected,if i remove tht iam able to get,otherwise to optimize thr are options to view ops even optimized,anyhow thanks iam able to clear this out,
Re: questasim-doubt hi ,iam able to get rid of this,there is an option of optimize the design a checkbox,which was selected,if i remove tht iam able to get,otherwise to optimize thr are options to view ops even optimized,anyhow thanks iam able to clear this out,