Problem with getting output signals in qsim (Verilog)

[vinodkumar]

Hi ,iam unable to get the output signls in the objects,waveform for verilog in qsim,for the simple code written has shown below:

module ffpos(clk, d, q);
input clk;
input d;
output q;
reg q;

always@(posedge clk)
begin
q<=d;

end

endmodule

IS there any error in the code written,but iam getting evrything well for VHDL.wht could be the reason.

 

[avimit]

Re: questasim-doubt

Hi
I can only say there is nothing wrong with the code.
Kr,
Avi
http://www.vlsiip.com

 

[vinodkumar]

Re: questasim-doubt

hi ,iam able to get rid of this,there is an option of optimize the design a checkbox,which was selected,if i remove tht iam able to get,otherwise to optimize thr are options to view ops even optimized,anyhow thanks iam able to clear this out,