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Problem with getting output signals in qsim (Verilog)

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vinodkumar

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Hi ,iam unable to get the output signls in the objects,waveform for verilog in qsim,for the simple code written has shown below:

module ffpos(clk, d, q);
input clk;
input d;
output q;
reg q;

always@(posedge clk)
begin
q<=d;

end

endmodule

IS there any error in the code written,but iam getting evrything well for VHDL.wht could be the reason.
 

vinodkumar

Full Member level 5
Joined
Oct 5, 2006
Messages
251
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12
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24
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3
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Re: questasim-doubt

hi ,iam able to get rid of this,there is an option of optimize the design a checkbox,which was selected,if i remove tht iam able to get,otherwise to optimize thr are options to view ops even optimized,anyhow thanks iam able to clear this out,
 

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