problem with folded coscode fully differential opamp

[manissri]

coscode

hi .all
plz help..
i am desiinging pipelined adc ...
for which i have to desing an opamp with 12.5ns settling time ..
for this i am using folded cascode full differential architecture.
the specification is given to me is settling time is of 12.5 ns.
by this settling time i calculated the worst slew rate of (vdd/2)/(ts/10) as given in holberg book that if slew rate is not given and settlilng time is given then make the worst slew rate by settling time specs.
so by this slew rate i got current of about 5 ma in the tail of folded cascode fully differential opamps. so by this much current i am getting a huge sizes of my opamps.
so sir my question is how i proceed to calculate the current in tail by given settling time specs ..
i am unable to resolve it ...
plz help ...
my vdd is 5v and vss is 0v

 

[Humungus]

Total settling time is obtained as the addition of the slewing time plus the exponential settling. You have to decide what portion of your transfer will be slewing and what will be exponential settling. Also settling time is referred to a given error. It is not the same to settle to 1% than to do it to 0.01%.

In folded cascode, you must remember that there are two slew rates. The internal one, dominated by the slewing of the input of the cascoded mirrors, and the external slew rate governed by the slewing of the output stage.

Also, for a given transition frequency, folded cascode amplifiers give you two possible solutions.

 

[ocarnu]

You dindn't say the load, the precision, and the feedback factor. For 10b you need 7t in the exponential part.
Anyway 5mA in the tail (means 10 mA for the entire amplifier) seems resonable for 12ns if you have a load in the range of pF and the best case feedback factor, close to 1 (but I think you have 0.5).

 

[manissri]

hi ocarnu..
my load is 2.5pf.
and the pipelind adc is 12 bit ...
so any solultion u have to reduce this much of current and getting the same specs like 12..5 ns settling time. coz due to this heavy current am getting huge W/L and power dissipation
hope u understand my query
waitng for ur reply
manish

 

[ocarnu]

If you get a solution to obtain speed and precision without power, the Nobel prize is yours . Get used to it: 12 bits at this frequency require some power. You want the time costant around 1.5ns or so, β I guess is around 0.3, t=1/wβ, w=350MHz is the minimum unity gain freq. you can hope for. w=gm/CL, gm=5.5mS. Now, this is not that much, but it depends on technology (Vdd=5V, I suppose u use an old one). Use minimum length transistors in the input diff pair. Hope I didn't make a mistake. Slew rate will worsen the things a little bit, u might want to take some margin.

 

[okguy]

12bits with a 5V process :?: :!:
Which process are you using? Which is your Kn of your NMOS?
To my knowledge, you need at least 0.18um process.
Any other opinion ?

 

[ocarnu]

Resolution and process have nothing in common. You can obtain "any" resolution you want from any process. Only speed and area are a function of the process.

PS: I know a company who makes 16-18 bits ADC in 0.6 process.

 

[manissri]

hi ocarnu..
my B= cf/(cs+cf+copamp) where cs = cf = copamp
then B=1/3.
and for 0.1% setting the ts(setting time) = 7t. ( where ts=12.5ns)
so the ugb for this settling time is t=1/BW
i am getting ugb around 270mhz.
so gb=gm/cl
cl=2.5pf.
and getting gm = approx 4.0ma/v
and gm=2*Id/Vdsat
putting Vdsat=100 mv
i am getting Id = aprrox 240ua. in (differential pair)
so my tail current is around 680ua.

my question is that will i get 12.5ns setting time.
will the slew rate not limit this small current ???
plz answer ..
manish

 

[ocarnu]

It will but maybe not much. BTW, 7t is for 10 bits as i remember, for 12 you need more. Now, you should just compute how much it takes for your op amp to slew over the entire range. From C*U=I*t, I is the currnet flowing in the cap, C is load cap, U is maximum output variation (max. amplitude from - to +). Now, if it takes only 1*t or so to slew, it will not impact the settling trime too much. However, if it is too much (like if you designed the current in the output branch of the folded cascode too small), consider adding some clamping devices to improve slewing (see Martin's book).

 

[arpit_655]

check the phase margin...PM more than 70 deg slows the response.
UGF requirement is for small signal settling(linear settling). in slewing, the current available to charge the load cap ,decides ts.
refer to the "CMOS analog IC design" by razavi