Problem simulating Veriloga in spectre in cadence

[Zubair Alam]

Dear all,
I have implemented stanford CNFET model in veriloga(no errors found) then made a symbol(no errors found). Then i wanted to use it in circuit(dc sweeping/transient analysis) to see whether the veriloga does what it is supposed to do. When i try to simulate it.it gives me the following error:
"ERROR: Netlister: unable to descend into any of the views defined in the view list: "spectre cmos.sch schematic veriloga" for instance I0 in cell......."

Can someone help me out. I am a Newbie to Cadence.

Thanks and Regards,
Zubair.

 

[dick_freebird]

What is instance I0? Start there, find it in library manager
and see what views -do- exist.

You should have a veriloga view, and a veriloga.va file as
well. I would guess maybe you don't have the veriloga
view (you might copy or symlink the symbol for that).

 

[Zubair Alam]

I0 is a ncnfet. But i already created the veriloga view where veriloga.va,NCNFET_L2.va and NCNFET_L1.va files are there. Then I created the symbol and no errors were found.
But now when i am trying to use that symbol in circuit the simulation is giving error. What could be the problem??

 

[dick_freebird]

Change your switch view list to put 'veriloga' before 'symbol'
and 'cdsSpice' and then try to switch-view (descend) into
the instance. If it's really in the right place to be found, this
should open you a text editor with the verilog.va code. If
this fails, you are on the track that Spectre netlisting is failing
to traverse, at least, and can look around in context.

By way of debug, you might try making a schematic rep of
the CNFET (like a crude JFET generic inside a set of pins)
and see how that runs. Then if this works (functionally)
set up a config view for the sim testbench schematic
(Hierarchy Editor) and kick off your simulations from this
view instead, so you have both schematic based simulation
and fine grained control over view-switching. If hierarchy
editor / config view fails to show your veriloga, that would
have to be a clue; if it finds it, then at least you can
toggle around and control netlist hierarchy / view switching.

 

[Zubair Alam]

I have already changed my switch view list and inserted 'veriloga'. In that list there is no 'symbol' or 'CdsSpice'. But when I added veriloga and symbol in that list the simulator ignores the instance and gives the simulation showing only the input.no result for the ncnfet.

 

[dick_freebird]

If I understand you correctly, you are just not seeing
simulation results for the "ncnfet" terminals? I think I
ran into that many years ago, and found I needed to
put some more traditional analog element in series
with the veriloga output (like a trivial 'res') to force
the veriloga<->spectre interface to bring out the
node data properly. Try putting a resistor between
each ncnfet terminal and whatever it's attached to
now, and probe at the outboard ends of them (or
current, through).

 

[Zubair Alam]

Thanks freebird. I solved the problem.
But a new problem has arised:1. with ncnfet,pcnfet i designed some logic gates. but now when i am giving same voltage at vdd(5 V) and gate(5v=logic 1(giving pulses 0 to 5v)) the dc analysis of spectre is not showing logical result.it is showing a ramp.but when i am using Vg>Vdd it is show correct logical result.why?

 

[dick_freebird]

Perhaps your pinchoff voltage is not appropriate to the ncnfet
device? Or even, FET species may be reversed (PFET vs NFET)?

I suggest beginning with (or going back to) testbenches for
DC I-V curves and making sure your device model matches
dvertised attributes.

An enhancement mode NFET on the high side, surely will
want Vg>Vdd if you want the VOH to approach Vdd and not
act as a source follower w/ voltage drop, instead.

 

[vieha007Electronic]

Thanks freebird. I solved the problem.
But a new problem has arised:1. with ncnfet,pcnfet i designed some logic gates. but now when i am giving same voltage at vdd(5 V) and gate(5v=logic 1(giving pulses 0 to 5v)) the dc analysis of spectre is not showing logical result.it is showing a ramp.but when i am using Vg>Vdd it is show correct logical result.why?

Dear Zubair Alam,

I am also importing the verilogA model of CNFET from Standford into Cadence. However I met some difficulties with doing this work. So I would like to aks you about the procedure that how can i do it.

I appreciate your helps. Thank you very much.

 

[Zubair Alam]

sorry for the late reply.
i guess you are using cadence.
1.go to virtuoso.
2.create a new cell view
3.select cell view type :veriloga
4.then copy the top level module(ncnfet_L3.va) contents/codes in the editor window,parallely go to the veriloga folder and create/copy the files parameters.vams,disciplines.vams,ncnfet,ncnfet_L2.va,ncnfet_L1.va.
5.save and exit from the editor window.
6.if you do it correctly it will ask you to create symbol.select yes.
7.then draw a symbol.
8.use the symbol to simulate.