problem in resisteance termination

[serma]

Hi i face a problem in resistance termination. my spec limit is 80 to 110 ohm. but in my pdk resistance variation is 20% so i cant able to attain it. do anybody know the circuit for attaining it without calibration.

 

[ZekeR]

Your choices are either:
A) Trim the resistor value
B) In production, throw away any chips that don't meet spec (bad idea)
Somewhere in your circuit, you need to have a known and well-defined V/I relationship; the chip can't do it by itself.

If you have many terminations, you can make things a little more space-efficient by using a single trim which simultaneously adjusts all of the terminations by the same amount. Another idea is to require an external resistor of known value, across which is expressed a reference voltage... This will generate a known current, which can be used by the chip to perform internal calibration.

 

[D.A.(Tony)Stewart]

Can you consider a process Design Kit tester. such as Ridgetop's for ATE
**broken link removed**
Then SOT or trim on test to match.
Otherwise, find the process variables that regulate the pdk resistance and improve source variances through pre-test wafer sorting or DOE ( Design of Experiments) using Taguchi methods to achieve 95Ω nom. with better than 15% tolerance. Ideally you want a Cpk>>1 for high yields.

Without more details, I can only suggest generalized solutions that worked for me.

At C-MAC we use laser trim methods for Ceramic ASICs at our sister plant in Sherbrooke designed by students for production.

 

[dick_freebird]

You could pull some process control data and see whether the
foundry is really that loose, or your modeling guys are just a
bunch of sandbagging sons of bizzles. If you have control
data then you may determine that you'd rather eat 5% yield
loss at wafer probe, than beat yourself up over a ghost that
shows up only occasionally (like, just when volume starts to
ramp, yeah).

Now on-chip termination sounds like a good thing, but you
should bet that your termination will have undesirable L, C
terms as a result. You should be very sure that the customer
is not willing to place the terminations off chip where they
have more control over PCB trace performance and access
to better, exact component values.