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[SOLVED] Problem in developing synthesizable verilog code

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er.akhilkumar

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Hello all,

I have a problem in writing an independent statement assigning 1-bit constant value to a reg type (not in always block) in module.

Here is the dummy code:

module one_bit (input a , output reg b);

assign b = 0; // is not synthesizable as b is of reg type
//always will not make sense in assigning permanent value

endmodule

Can anyone please help me in solving out this problem?

In VHDL I can simply write:
b <= '0'; // Permanently bound to ground as in VHDL there is no reg type std_logic is same for all
But in verilog I cannot write like above and I also cannot use assign statement as bit is of reg type.

Thanx
 

mail4idle2

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This should solve your issue
################################
module one_bit (input a , output b);

assign b = 0; // is not synthesizable as b is of reg type
//always will not make sense in assigning permanent value

endmodule
################################
 

ads_ee

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assign has to have a wire type.

module one_bit (input a, output wire b);

the wire is the default type as mail4idle2 showed in his example.

I would suggest going over a Verilog tutorial as you seem to have been a VHDL user.
 

dave_59

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This would have worked in SystemVerilog. It allows you to make a single continuous assignment to a reg variable.
 

er.akhilkumar

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Thanx for your replies. I knew that you will suggest me to replace type of "b" from reg to wire. But this is a dummy problem. Actually I have to develop a read/write memory-mapped register in which there is a parameter named as IMPLEMENT whose value tells the generate statement that which bits of "b" shall be output of flip-flop and the bits for which IMPLEMENT's value is 0 shall be permanently bound to 0.

As in case of register implementation "b" shall be always of type reg thats why I am trying to permanently assign 0 to the bits of register for which IMPLEMENT is 0.

Can you please help me solving this problem?
 

er.akhilkumar

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Friends, the problem has been solved. Thanks for your replies. What I have done is, I have declared the output as wire but I have declared a temporary signal of reg type inside the module. I used temporary reg type signal for register implementation and the bits for which flip-flop shall not be implemented are connected permanently to grounf using assign as output is of wire type.
 

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