I have problem adding dummy gates in two sides of my main RF transistor on the same RX area.
When I add dummy gates in two sides of the RF NMOS/PMOS transistors the LVS is not clean any more while I have considered the added transistors on the schematic.
In LVS log file it says: "1 Mal-Formed Device(s) detected."
This problem exists only in RF/triple-well devices not in nfet/pfet devices.
No, I gave up on that. I even contacted MOSIS in this regard, but the kit is designed in this way.
It is better to choose large devices and put them close to each other to solve the matching problem in this way if you can.
I just sent a requesting email right before seeing your reply. It is wield because in this way, almost no interleaved structures in triple well could be achieved in this kits.
But anyway, I guess I will do what you said, using large devices and putting them close.
No, I gave up on that. I even contacted MOSIS in this regard, but the kit is designed in this way.
It is better to choose large devices and put them close to each other to solve the matching problem in this way if you can.