LVS not clear while adding digital std cells into analog layout

[QuintonLi]

Hello every one.
I'm using SMIC0.13um CMOS tech, and its evry kind of std digital cell doesn't connect to power directly. In other words, the well net is isolated within the cell.

for example, here is the schematic of an invertor.


In manual it says we need to add FILLTIE cell to connect wells to power nets. I know that and I did that in the layout.
Wells are connected to the power nets in layout. However, in schematic, just as the pic shows, VPW & VNW are not pins that can be cited outside the std cell. Thus, I cannot connect VPW & VNW from the top level. And that causes the LVS to go wrong: In source there is "I0/VNW""I0/VPW"; but in layout they are directly connected to VDD & VSS, and that is the question.


So how can I fix this difference to clear LVS?

 

[dick_freebird]

Check your symbol for properties that want a net-name
which will be applied to those stupid "internal" isolation
nodes (which in the end will likely be merged in layout
for well-spacing-rule-sandbagging) and so you will need
to make sure all those invisible properties get the same.

As if "VPW" wasn't always going to be VSS and "VNW",
VDD. Who allows "hot wells"?

 

[QuintonLi]

Check your symbol for properties that want a net-name
which will be applied to those stupid "internal" isolation
nodes (which in the end will likely be merged in layout
for well-spacing-rule-sandbagging) and so you will need
to make sure all those invisible properties get the same.

As if "VPW" wasn't always going to be VSS and "VNW",
VDD. Who allows "hot wells"?

Hi dick.
Unfortunately, there's no such properties in std symbols.
I am wondering if there's a way to set global net names to "VNW""VPW", just as the typical "VDD!""VSS!".

 

[dick_freebird]

You can change those net labels to VNW! and VPW! to make them global.
But I think somewhere around that cell library should be some written-up
guidance about proper connection of these "inherited connections". In
fact that keyword-pair is worth chasing through the Cadence docs to see
how it's recommended to be done, just in case somebody decided to
listen to advice.

 

[k_90]

these are "inherited connections" driven by the pins at the levels above, so you won't get pins in the digital cell. From a layout point of view either use a tie cell that connects to the pwr/gnd or manually add p/n diff ties.