Problem - Dracula LVS resolution only 0.01um

[karnopas]

Hi All,

I have a problem doing LVS on Dracula and need your suggestion.

I drew a CMOS transistor width 1.405um in both schematic and layout (L=0.18um). However, Dracula LVS reports a mismatch.

It appears that Dracula had rounded the width in different ways, i.e. 1.40um in schematic and 1.41um in layout. It looks like Dracula have only 0.01um resolution.

The "scale" & "resolution" options were already set to 0.001.

How can I improve LVS resolution?

 

[crazy_analog]

Have you band the layout?
If you band layout, it is not correctly extracted transistor size.
Can you try straight pattern?

 

[waxtomato]

I am not sure your manufacture can make a resolution of 0.005um, why you have such a strange size?

 

[karnopas]

Thanks for your comments,

I shrink a layout from 0.35u to 0.18u technology using 0.52x factor. So, after shrinking 2.7um (it's a straight poly gate) and snap it to grid. Since the grid size specified in the document is 0.005, I got 1.405um

Karnopas