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design it with two cross coupled DFF in ring configuration and by CML (Current Mode Logic) Full Differential technology for higher speed.
be careful! single ended outputs have not 50 % duty cycle but differential ones have (since only have odd harmonics!)
for this block normally differential logic is used not single ended ones (for to noise immunity).
You can use a narrow bandpass filter to filter out the fundamental tone and reject the harmonics. Or use a flip-flop as the last divider, if a divide-by-two is feasible within the prescaler chain.
As i know there is no need to filter and also it is not possible to implement!
current realizable divider solutions are:
1.miller divide by two (very fast up to several GHz)
2.DFF ring divide by two (same as above when implemented by CML)
3.Injection Locked Frequency Divider, ILFD, (very very high speed even to 20 or 4 GHz sutable for narrow band applications but requires on chip inductor i.e more area but the power consuption is moderate or low!)
may be u mean the LC tank used in ILFD, if so, thats right!
Duty cycle is the fraction of the time the logic level is high compared to low. The question was about an expected perfect square wave output (high and low half the time each).
I think the duty cycle is decided by your architectures, not by the logic styles.
For example, if the pre-scale is divider by 4, it will be 50% duty clycle, if it is divided by 5, it will have 40% duty cycle.
Anyway,why do you need 50% duty cycle? Most of time It is the edge we care.
I think the duty cycle is decided by your architectures, not by the logic styles.
For example, if the pre-scale is divider by 4, it will be 50% duty clycle, if it is divided by 5, it will have 40% duty cycle.
Anyway,why do you need 50% duty cycle? Most of time It is the edge we care.
Usually the used trick is to divide by two the prescale output (of course you have to modify prescaler ratio) to get fifty percent duty cycle.
I hope it can help.
Mazz
You can use a narrow bandpass filter to filter out the fundamental tone and reject the harmonics. Or use a flip-flop as the last divider, if a divide-by-two is feasible within the prescaler chain.
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