PreCTS timing optimization

[kenambo]

Hi all,

I finished placement and when I ran preCTS timing analysis I got some violations in the path where scan clock is employed.

That is my data delay is unwantedly 15ns, so that i couldn't meet the timimg for these kind of paths, and every other pathgroups met good timing.

Do I miss some optimization commands like set_disable_timing.. like that.. I couldn't understand the root cause of this problem.

Please help me and if you need more details i can provide..

thanks....

 

[cyrax747]

Hi

Did you perform scan chain re ordering ? HFNS performed correctly ?

 

[kenambo]

Hi

I have done scan reordering but I haven't done HFNS so I will do that and ask my doubts after that

thanks for your idea....

Thanks

 

[kenambo]

Hi
when I gave the command scanReorder the window says no scan path here what does that mean?

thanks

 

[cyrax747]

hi,

extra data delay is due to any missing constraints like multicyle path or disable timing or false path.

 

[kenambo]

Hi

I analyzed the timing path. It is a strange path.

The Data path starts from scan_clk pin it goes through a MUX and some logic gates and reaches a Flip Flop.

Clock path also starts from the scan_clk pin and goes through the same MUX and then splits though some other logics
and then again reaches the Flip-Flop clock pin. But clock timing arc is taken as trailing edge.

the above is the scenario of my path.

The problem is Data delay for the first MUX is 13ns but clock delay after the same first MUX is 0.

I hope you understand this scenario. Have you seen this kind of path before? If so, can you please share what I have to do?

All the violating paths have similar problem .. so If we solve this.. I can get no violations in Pre-CTS stage.

Thanks.

 

[kenambo]

and also the fanout is too large as 3000 nets.. To do high fanout synthesis, i just add the constraint

set_max_fanout 10 [current design]

and do the placement again? or I can add this constraitn to the already placed design.. Please clarify?

thanks

 

[cyrax747]

hi

for HFNS create_buffer_tree is the command.
set_max_fanout is fanout is the number of cells drived by one output signal.this way it differs.

 

[kenambo]

Hi

While I am doing hfn synthesis I found an error it says 2 nets have no driver so it showed error and abort.

The error code is (ENCSYT-17015) can you please help me out?

thanks.