power ring width of memory

[ys82]

hi
I would like to know how to decide the width of memory power ring when using artisan memory compiler?
Thanks!

 

[MarcS]

Calculate the maximum instantaneous switching current, then look up the maximum voltage drop limit and the resistance per square of the metal layer. Then simply apply Ohm's law. Then add a generous safety factor.

As a final check, make sure that the wire is wide enough to keep the current below the maximum current density limit.

The hard part is determining the maximum current, which depends on you correctly assessing what transition will cause the maximum switching current. You can verify your results with power analysis tools (Apache, Sequence, Synopsys, ...)

 

[ys82]

Calculate the maximum instantaneous switching current, then look up the maximum voltage drop limit and the resistance per square of the metal layer. Then simply apply Ohm's law. Then add a generous safety factor.

As a final check, make sure that the wire is wide enough to keep the current below the maximum current density limit.

The hard part is determining the maximum current, which depends on you correctly assessing what transition will cause the maximum switching current. You can verify your results with power analysis tools (Apache, Sequence, Synopsys, ...)

Do you mean that I need to calculate the resistance of memory's power-ring, then using following formula to see Whether the power-ring width is ok:
(peak current) x (resistance of memory's power-ring) < maximum voltage drop limit
But when I using memory compiler to generate memory , It give a too big peak current in its parameter table view.

 

[MarcS]

Hi:

I apologize for being a bit too brief in my first posting. You are really worried about two problems: Not exceeding the maximum current density and not exceeding the maximum voltage-drop limit. The power ring must be sized so as to satisfy both these requirements.

Both problems require you to determine the current in every wire segment of the power network, from the source(s) to the sinks (power connections on each transistor). This is a looped network problem, so Ohm's law is applicable on a segment per segment basis, but you need an analog simulator to solve the network problem. This is not really something you can do by hand for real designs - that's why everybody uses specialized voltage drop analysis tools for this.

If you do not have access to such tools, then you need to fall back on rules of thumb or try to model the power ring in Spice yourself. One simplification that is sometimes used is to not consider every transistor individually, but to treat an entire row of transistors as one big current sink.

You also say the memory compiler calculates a peak current that is too big (how do you know it's too big?). The problem may be the compiler's assumtion on what the worst case activity is. Is it assuming, for example, that each and every transistor in the entire memory could be switching at exactly the same time? Yeah, that will give you a very big peak current, but it seems very pessimistic. What is the realistic worst case?

Unless you have access to an voltage drop analysis tool, your best bet is to ask someone who has designed a similar memory before and see what wire width they used (and ask if it worked ). Often designers simply guess at a width that seems safely big enough to handle whatever the vaguely estimated current may be, and then hope their safety margin was big enough.

 

[ys82]

memory compiler can generate the spec of memory, there is a table for some parameter(include peak current). Is there a effective way to generate memory with appropriate power-ring at the beginning of Design

 

[jbeniston]

Have you read the documentation that comes with the compiler? I believe it has a section on this subject.