I have synthesized my design using design complier.
the power report looks like
Cell Internal Power = -69.8378 pW (100%)
Net Switching Power = 0.0000 uW (0%)
---------
Total Dynamic Power = -69.8378 pW (100%)
Cell Leakage Power = 795.0621 nW
Can any one tell me why the power is in negative.I am using power gating technique.
And also my timing report is empty.
I never had this kind of issue. I would suggest to do a check_design and see the warnings, also check for any black-boxes in design. If everything works fine then use "-cell -hier " options and localize the bug
Cell Internal power depends on direction in which Current is drawn by the active device(transistor).
First check the liberty file of std cell & check for fall_power & rise_power of any cell in your design that has reported negative power. that should give u a clue to proceed further
Is clock gating enabled ?
To me it looks like an issue in the calc.. of the code of clock gating
My strong guess is that it would occur if - the percent diff of total toggle rate for all ungated flops vs. total toggle rate for all gated flops…
A quick check would be to write a small tcl code to calculate the power for ungated flops vs gated flops depending on the equation mentioned in the docs on how it uses probablity and toggle count to calculate dynamic power.
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Is clock gating enabled ?
To me it looks like an issue in the calc.. of the code of clock gating
My strong guess is that it would occur if - the percent diff of total toggle rate for all ungated flops vs. total toggle rate for all gated flops…
A quick check would be to write a small tcl code to calculate the power for ungated flops vs gated flops depending on the equation mentioned in the docs on how it uses probablity and toggle count to calculate dynamic power.