Power Ground Pad Placement in IO Ring

[xyz348]

Hi,

We are currently designing an SoC and have a question on sequence of VDD, GND pad placement in IO-Ring. Could anyone suggest on which option is best? and any reasons for it?

1. Sequence of : SIGNAL-IOVDD-SIGNAL-IOVSS-SIGNAL-COREVDD-SIGNAL-COREVSS
2. Sequence of : SIGNAL-IOVDD-IOVSS-SIGNAL-SIGNAL-COREVDD-COREVSS-SIGNAL
3. Sequence of : SIGNAL-SIGNAL-IOVDD-IOVSS-COREVDD-COREVSS-SIGNAL-SIGNAL


As per my understanding I wanted to go with #1, but would like to hear from experts on if there is any return-current-path that I need to care-about during pad-placement.

Please note that power-stripes are going to be in the fashion of "VDD-VSS" with minimal spacing for shortest return-current-path.

thanks in advance.

 

[hennyjia]

There's no hard rules for the P/G pad placement. But you need to follow some requirements for some specified pad cells( refclk, reset), you'd better put VSS around them for noise shielding.
And you also need to follow the ESD rules and also meet the IR-drop/EM requirements, both of them will impact the P/G pad placement.

In general, you also need to meet the SSO.