tariq786
Advanced Member level 2
multicycle sdf simulation
I am getting this error in post synthesis verilog simulation of AES core. Design Compiler synthesized the design correctly without any errors with a period constraint of 5ns( 200 MHZ) .
When i ran post synthesis verilog simulation, even with a period of 20ns (4 * 5 ns), i still get get the following error because of which the output is xxxxxxxxxxxxxxxxxxxxxxx.
Error: tsmc18t.v(6551): $hold( posedge CK &&& (flag == 1):30 ns, negedge D:30 ns, 500 ps );
# Time: 30 ns Iteration: 2 Instance: /test/u0/u0/r0/\out_reg[31]
Note that when i increase the period to 30ns (i.e. by a factor of 6), the error goes away. But i am wondering why is there an increase in the frequency by a factor of 6. This makes me think that Design Compiler grossly underestimates the clk periode?
Can some body help please so that i am able to run the post synthesis verilog simulation close to the frequency of 200 MHZ(i.e. 5ns) reported by Design Compiler.
I also checked with PrimeTime and it also had no problem with period constraint of 5ns.
Thanks a lot in advance
I am getting this error in post synthesis verilog simulation of AES core. Design Compiler synthesized the design correctly without any errors with a period constraint of 5ns( 200 MHZ) .
When i ran post synthesis verilog simulation, even with a period of 20ns (4 * 5 ns), i still get get the following error because of which the output is xxxxxxxxxxxxxxxxxxxxxxx.
Error: tsmc18t.v(6551): $hold( posedge CK &&& (flag == 1):30 ns, negedge D:30 ns, 500 ps );
# Time: 30 ns Iteration: 2 Instance: /test/u0/u0/r0/\out_reg[31]
Note that when i increase the period to 30ns (i.e. by a factor of 6), the error goes away. But i am wondering why is there an increase in the frequency by a factor of 6. This makes me think that Design Compiler grossly underestimates the clk periode?
Can some body help please so that i am able to run the post synthesis verilog simulation close to the frequency of 200 MHZ(i.e. 5ns) reported by Design Compiler.
I also checked with PrimeTime and it also had no problem with period constraint of 5ns.
Thanks a lot in advance