Are you getting a lot of timing-check violations in your simulation? You need to supply us with more info. Your VCS log (compilation-time & run-time) would help alot.
Are you back-annotating your sdf file? If so, then you need to find all your multi-flop synchronizers in your netlist and disable them. If you haven't done this, it will cause X's in your simulation. There is a couple way you can do this. You can disable them by using VCS's feature that disable timing check on an instance or edit the SDF file on those instances and zero out the values (setup/hold/...).
I highly recommend you first do your netlist simulation without back-annotation and with all timing-check disable, and all gate delay disable. In effect, you're only doing functional simulation on your netlist, very similar to your RTL simulation. So the result should be what you would get in your RTL simulation. If this works, then I would next enable gate delay, but still without timing checks enabled This most likely mean you need to change your timescale because now the gate delay of your lib cell has ps resolution. I typically use 1ns/1ps resolution for netlist simulation, and should be good for your's also. If your netlist with gate delay simulation without timing check works, then next I would enable the timing check. For this, it just uses the default timing values (setup/hold/etc.) in your library cells, which is not as accurate as the ones in your sdf file, which is after PAR. But this is fine for this step. Anytime you enable timing-check, you will get alot of timing violations if you don't disable the timing check on your sync flops. You need to manually disable them. You will know where they're located at when you running the simulation and you get a bunch of timing violations in your VCS log file. The last step is to back annotate your sdf file and re-run your simulation.
The following compile-time options does the following:
+nospecify : Disable the specify block in the gate, which means all timing checks will be disabled, as well as the gate delay.
+notimingcheck : Disable the timing checks only. You still have gate delay.
I can take a look at your VCS log file if you like.
- Hung