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Post-synthesis gate-level VCS simulation (race condition)

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Newbie level 5
Aug 26, 2009
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post synthesis gate level simulation

Short version:

How to configure VCS to understand multiple clocks for a gate-level simulation after clock tree synthesis and routing?

Long version, with details:

Are there any special tricks/command-line options necessary for running a post-synthesis gate-level simulation in VCS? After synthesis (specifically, after CTS and routing), a simple shift register in my design exhibits a certain race condition.

Specifically, the single clock to the shift register is being split/buffered as multiple clock inputs, distributed to the 32 D flip-flops comprising the register. Although each clock can be traced back to the same root of the clock tree, I think the multiple clocks are being "triggered" or added to the VCS event queues in an unexpected order. As a result, one particular bit in the register shifts early/incorrectly.

Are there commands during clock tree synthesis that I can use to aid the VCS simulation later? Or alternatively, am I using the right flags in VCS? Relevant details:

- everything is written in Verilog
- design works fine pre-synthesis, and is fine right before CTS, but the generated netlist after CTS exhibits this behavior
- using Synopsys CAD flow: Design Compiler (Y-2006.06-SP6) and Astro (Z-2007.03-SP10), with a 90-nm TSMC process
- VCS (B-2008.12) with the following flags: -sverilog +v2k +lint=all -v <path>/tcbn90ghp.v -y <path>/src_ver +libext+.v+ -timescale=100ps/100ps +timopt=300ps

Thanks in advance for your help!

gate level synthesis

Try turning on -debug or -debug_all for the SAKE of shutting down optimization and see if that helps. If yes, then we can further nail it down to specific code.

Best is if it reproduced in a small testcase - the scenario you've described looks recretable, but does that show race problem?

Ajeetha, CVC

vcs +race condition

Make sure design is timing clean after CTS i.e. no timing violations. Also you need to use SDF when you do gate level simulation to annotate timing delay properly.


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