triquent
Full Member level 3
Confused about the post synthesis functional and timing simulation results by Synopsys Design Compiler. I tried to simulate and synthesize a decoder. The code is very simple.
module decode (in, out);
input [3:0] in;
output [15:0] out;
assign out = 1'b1 << in;
endmodult
part of fixture code:
`timescale 1ns/10ps
............
$monitor($time," in=%b(%d), out=%b", in, in, out);
............
in = 4'b0000;
#100 in = 4'b0001;
#100 in = 4'b0010;
#100 in = 4'b0011;
#100 in = 4'b0100;
#100 in = 4'b0101;
#100 in = 4'b0110;
post synthesis functional and timing simulation results by DC COmpiler:
0 in=0000( 0), out=xxxxxxxxxxxxxxxx
1 in=0000( 0), out=0xxxxx0xx0xxxxxx
1 in=0000( 0), out=0000000x000x0xxx
1 in=0000( 0), out=000000000000000x
1 in=0000( 0), out=0000000000000001
100 in=0001( 1), out=0000000000000001
101 in=0001( 1), out=0000000000000011
101 in=0001( 1), out=0000000000000010
200 in=0010( 2), out=0000000000000010
201 in=0010( 2), out=0000000000000000
201 in=0010( 2), out=0000000000000100
300 in=0011( 3), out=0000000000000100
301 in=0011( 3), out=0000000000001100
301 in=0011( 3), out=0000000000001000
400 in=0100( 4), out=0000000000001000
401 in=0100( 4), out=0000000000000000
401 in=0100( 4), out=0000000000010000
500 in=0101( 5), out=0000000000010000
501 in=0101( 5), out=0000000000110000
501 in=0101( 5), out=0000000000100000
600 in=0110( 6), out=0000000000100000
601 in=0110( 6), out=0000000000000000
601 in=0110( 6), out=0000000001000000
You can see the output is not corresponding to the input. There are some delay fro the output. And some place have some error. Do you think this synthesis is successful or is not? Is the output delay corresponding to input is permittable in the design?
module decode (in, out);
input [3:0] in;
output [15:0] out;
assign out = 1'b1 << in;
endmodult
part of fixture code:
`timescale 1ns/10ps
............
$monitor($time," in=%b(%d), out=%b", in, in, out);
............
in = 4'b0000;
#100 in = 4'b0001;
#100 in = 4'b0010;
#100 in = 4'b0011;
#100 in = 4'b0100;
#100 in = 4'b0101;
#100 in = 4'b0110;
post synthesis functional and timing simulation results by DC COmpiler:
0 in=0000( 0), out=xxxxxxxxxxxxxxxx
1 in=0000( 0), out=0xxxxx0xx0xxxxxx
1 in=0000( 0), out=0000000x000x0xxx
1 in=0000( 0), out=000000000000000x
1 in=0000( 0), out=0000000000000001
100 in=0001( 1), out=0000000000000001
101 in=0001( 1), out=0000000000000011
101 in=0001( 1), out=0000000000000010
200 in=0010( 2), out=0000000000000010
201 in=0010( 2), out=0000000000000000
201 in=0010( 2), out=0000000000000100
300 in=0011( 3), out=0000000000000100
301 in=0011( 3), out=0000000000001100
301 in=0011( 3), out=0000000000001000
400 in=0100( 4), out=0000000000001000
401 in=0100( 4), out=0000000000000000
401 in=0100( 4), out=0000000000010000
500 in=0101( 5), out=0000000000010000
501 in=0101( 5), out=0000000000110000
501 in=0101( 5), out=0000000000100000
600 in=0110( 6), out=0000000000100000
601 in=0110( 6), out=0000000000000000
601 in=0110( 6), out=0000000001000000
You can see the output is not corresponding to the input. There are some delay fro the output. And some place have some error. Do you think this synthesis is successful or is not? Is the output delay corresponding to input is permittable in the design?