My netlist is as following: what's wrong with that?
how to get a combinational 16:1 Mux with 16 bit inputs and 4 bit select after synthesis? how to wirte the code?
module decode ( in, out );
input [3:0] in;
output [15:0] out;
wire n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157;
N2P U37 ( .X(n146), .A1(in[1]), .A2(in[2]) );
N2P U38 ( .X(n147), .A1(in[1]), .A2(n156) );
N2P U39 ( .X(n148), .A1(in[2]), .A2(n157) );
N2P U40 ( .X(n149), .A1(n156), .A2(n157) );
N2P U41 ( .X(n150), .A1(in[3]), .A2(in[0]) );
N2P U42 ( .X(n151), .A1(in[3]), .A2(n154) );
N2P U43 ( .X(n152), .A1(in[0]), .A2(n155) );
N2P U44 ( .X(n153), .A1(n154), .A2(n155) );
N2P U45 ( .X(out[15]), .A1(n146), .A2(n150) );
N2P U46 ( .X(out[14]), .A1(n146), .A2(n151) );
N2P U47 ( .X(out[13]), .A1(n148), .A2(n150) );
N2P U48 ( .X(out[12]), .A1(n148), .A2(n151) );
N2P U49 ( .X(out[11]), .A1(n147), .A2(n150) );
N2P U50 ( .X(out[10]), .A1(n147), .A2(n151) );
N2P U51 ( .X(out[9]), .A1(n149), .A2(n150) );
N2P U52 ( .X(out[8]), .A1(n151), .A2(n149) );
N2P U53 ( .X(out[7]), .A1(n146), .A2(n152) );
N2P U54 ( .X(out[6]), .A1(n153), .A2(n146) );
N2P U55 ( .X(out[5]), .A1(n148), .A2(n152) );
N2P U56 ( .X(out[4]), .A1(n148), .A2(n153) );
N2P U57 ( .X(out[3]), .A1(n147), .A2(n152) );
N2P U58 ( .X(out[2]), .A1(n147), .A2(n153) );
N2P U59 ( .X(out[1]), .A1(n152), .A2(n149) );
N2P U60 ( .X(out[0]), .A1(n153), .A2(n149) );
V1N U61 ( .X(n154), .A(in[0]) );
V1N U62 ( .X(n155), .A(in[3]) );
V1N U63 ( .X(n156), .A(in[2]) );
V1N U64 ( .X(n157), .A(in[1]) );
endmodule
whizkid said:
Is the output delay corresponding to input is permittable in the design?
I guess its not , unless your design is sequential..
You can achieve the same results by using a combinational 16:1 Mux with 16 bit inputs and 4 bit select. But ur code needs to be changed.
Please post ur NETLIST for omre comments..
rgds
WHIZKID