post layout simulation

[p_shinde]

hi,


which tool is used if one does post layout simulation in semicustom flow design????


thanks,reply soon.
Prasad

 

[bastos4321]

Use Hsim to do the post layout simulations.

Bastos

 

[p_shinde]

hi,

does that tool takes the GDSII input?

thanks,
Prasad

 

[tarkyss]

you must extract the netlist from you gdsii file firstly(star-rcxt can do that)
and then simulation
a lot tools can do that
such as nanosim of synopsys

 

[p_shinde]

then whats the difference between this netlist and the netlist used while starting the design got from PKS, DC like tools......

is that only its post layout netlist, so would there be any changes in that like what? the same post layout netlist which we give for physical verification?


thanks,
Prasad

 

[tarkyss]

there are RC parameters in the netlist

 

[tnmk]

you can use Synopys Nano sim for post layout simulation. but is not so accurate as your hspice

 

[spauls]

are you looking for full chip simulation or some specific areas of chip ?

Added after 22 seconds:

are you looking for full chip simulation or some specific areas of chip ?

 

[p_shinde]

full chip simulation , is it possible????


thanks,
Prasad

 

[tarkyss]

it depends on the scale of your chip and what you want to check.
post layout simulation is very slow

 

[p_shinde]

is there any different tool for post layout simulation???

 

[sp_sara]

Hi
you can get a verilog netlist after layout and simulate it's behavior with some simulation tools like modelsim and nclaunch.then you have to compare it with post synthesis simulation