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you must extract the netlist from you gdsii file firstly(star-rcxt can do that)
and then simulation
a lot tools can do that
such as nanosim of synopsys
then whats the difference between this netlist and the netlist used while starting the design got from PKS, DC like tools......
is that only its post layout netlist, so would there be any changes in that like what? the same post layout netlist which we give for physical verification?
Hi
you can get a verilog netlist after layout and simulate it's behavior with some simulation tools like modelsim and nclaunch.then you have to compare it with post synthesis simulation
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