ianalog
Junior Member level 1
sdf_annotate
HI,all,
Now I would like to run a post-layout simulation with sdf file back-annotated. I add the sdf file into my final gate level netlist (by astro) and using the NC-verilog simulator. The tool of plant and route is the Astro. I got the simulation result of gate-level netlist of the post-synthesis with this way. but, the post-layout result is not getten. why is this reason?
my code is shown as :
module top_test;
reg RESET, CLK, IN;
wire [5:0] dout;
parameter STEP=100;
SIN_POUT SIN_POUT(RESET,IN,CLK,dout);
initial
begin
$sdf_annotate("SPCELL.SDF",SIN_POUT);
//$sdf_annotate("ser_pa.sdf",SIN_POUT);
end
always #(STEP/2) CLK=~CLK;
initial
begin
RESET=0;CLK=0;
......
verification file include the source code, testbench, and SDF file. The simulation result with sdf file is same the result without the sdf file. why? please.
HI,all,
Now I would like to run a post-layout simulation with sdf file back-annotated. I add the sdf file into my final gate level netlist (by astro) and using the NC-verilog simulator. The tool of plant and route is the Astro. I got the simulation result of gate-level netlist of the post-synthesis with this way. but, the post-layout result is not getten. why is this reason?
my code is shown as :
module top_test;
reg RESET, CLK, IN;
wire [5:0] dout;
parameter STEP=100;
SIN_POUT SIN_POUT(RESET,IN,CLK,dout);
initial
begin
$sdf_annotate("SPCELL.SDF",SIN_POUT);
//$sdf_annotate("ser_pa.sdf",SIN_POUT);
end
always #(STEP/2) CLK=~CLK;
initial
begin
RESET=0;CLK=0;
......
verification file include the source code, testbench, and SDF file. The simulation result with sdf file is same the result without the sdf file. why? please.