post-layout simulation +sdf_annotate

[ianalog]

sdf_annotate

HI,all,
Now I would like to run a post-layout simulation with sdf file back-annotated. I add the sdf file into my final gate level netlist (by astro) and using the NC-verilog simulator. The tool of plant and route is the Astro. I got the simulation result of gate-level netlist of the post-synthesis with this way. but, the post-layout result is not getten. why is this reason?

my code is shown as :

module top_test;
reg RESET, CLK, IN;
wire [5:0] dout;
parameter STEP=100;

SIN_POUT SIN_POUT(RESET,IN,CLK,dout);
initial
begin
$sdf_annotate("SPCELL.SDF",SIN_POUT);
//$sdf_annotate("ser_pa.sdf",SIN_POUT);
end

always #(STEP/2) CLK=~CLK;
initial
begin

RESET=0;CLK=0;
......
verification file include the source code, testbench, and SDF file. The simulation result with sdf file is same the result without the sdf file. why? please.

 

[aslijia]

$sdf_annotate

sometimes your library's version don't match the version of the tool you use. i have met this problem. i solute it as follow:
my_script
......
......
write_sdf -v 1.0 *****
..........

that is, add the "-v x.x", the version of your tool

hope it is helped for you

 

[aji_vlsi]

when and how to use $sdf_annotate

verification file include the source code, testbench, and SDF file. The simulation result with sdf file is same the result without the sdf file. why? please.

Hi,
So are you saying that you are not sure whether SDF annotation really occured? Usually NC gives message about SDF annotation during simulation at time 0 - do you see that in your log? If not then there is something wrong. If you do see them, then perhaps every thing is well and good and your design is meeting the timing - atleast for the given testcase/path being excercised by this test.

Make sure you don't have options like:

-notimingcheck
-nospecify

These will turn off timing checks and spoil the usage of SDF to start with.

Regards
Ajeetha, CVC
www.noveldv.com

 

[ianalog]

sdf_annotate verilog

Thank you , aslijia and aji_vlsi.
write_sdf -v 1.0 *****
sorry, I dont understand what it mean? I didnot use this command. please tell all of .

I check my log.
the log file give a message of timing violation.
Warning! Timing violation
$hold( negedge XC &&& D:2000240 PS, posedge XR:2000440 PS, 21 : 210 PS );
File: /project/VDEC/rohm035u/lib/Verilog/ROHM035.v, line = 967
Scope: top_test.SIN_POUT.\U1/OUT_REG[0]
Time: 2000440 PS
but the report of astro is Timing met. why?
how will I fix my P&R or other question?
Thank you very much!

mark. lee

 

[spauls]

$sdf_annotate(

AStro uses STA technique,
Its better view the waveformand analyse

 

[flyer]

Re: sdf_annotate verilog

Thank you , aslijia and aji_vlsi.
write_sdf -v 1.0 *****
sorry, I dont understand what it mean? I didnot use this command. please tell all of .

I check my log.
the log file give a message of timing violation.
Warning! Timing violation
$hold( negedge XC &&& D:2000240 PS, posedge XR:2000440 PS, 21 : 210 PS );
File: /project/VDEC/rohm035u/lib/Verilog/ROHM035.v, line = 967
Scope: top_test.SIN_POUT.\U1/OUT_REG[0]
Time: 2000440 PS
but the report of astro is Timing met. why?
how will I fix my P&R or other question?
Thank you very much!

mark. lee

Hi ianalog,
I meet the similar case. There is no violation When I do P&R. But the NClaunch generates some setup and hold warnings when I do postlayout simulation. Have you fixed your problem? And how to fix it? Thanks a lot.