posedge and negedge in verilog always block

sunidrak · May 14, 2013

hi

can anybody explain

always @(posedge clk or negedge rst)
if(rst)
q<=0;
else
q<=d;
.
.
.
if reset is active high and and i want apply it as posedge . . is it possible to do

regards
Sunil

FvM · May 14, 2013

The correct syntax is

Code:

always @(posedge clk or posedge rst)
if(rst)
q<=0;
else
q<=d

for active low reset

Code:

always @(posedge clk or negedge rst)
if(!rst)
q<=0;
else
q<=d;

Please consider that the required Verilog syntax for asynchronous register control hasn't to do with edges, it's actually describing level triggering.

posedge and negedge in verilog always block

sunidrak

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FvM

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posedge and negedge in verilog always block

sunidrak

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