posedge and negedge in verilog always block

[sunidrak]

hi

can anybody explain


always @(posedge clk or negedge rst)
if(rst)
q<=0;
else
q<=d;
.
.
.
if reset is active high and and i want apply it as posedge . . is it possible to do



regards
Sunil

 

[FvM]

The correct syntax is

always @(posedge clk or posedge rst)
if(rst)
q<=0;
else
q<=d

for active low reset

always @(posedge clk or negedge rst)
if(!rst)
q<=0;
else
q<=d;

Please consider that the required Verilog syntax for asynchronous register control hasn't to do with edges, it's actually describing level triggering.