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Ports missing during LVS

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crystal

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calibre lvs check unattached label

I was trying to run LVS for a simple transistor (schematic vs layout). However I have this error of no ports found in the layout source during Calibre LVS.

Layout Source

Ports: 0 5

Nets: 17 11

Instances: 10 1


Kindly advise.

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PaloAlto

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You have to put the ports as labels. Put them on top of the metal using as layer the metal layer too, the exact layer depends on the technology. The text will be the name of the port.
 

SP24

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you can also automatically generate the labels for the ports using the option
'Generate labels from pins'.
 

crystal

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I've tried both methods but the LVS report is still the same. No port detected.
 

SP24

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The calibre manual says,
Unattached ports occur when the port layer does not appear in Connect, Attach, or Label Order statements; or there is no geometry that the port can be attached to at the port location.

I think you need to cross check the port layers whether they are either in pin or drawing.
Make sure the ports are identical in layout and schematic.
This way it should work.
 

crystal

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The pin layers are in drawing layers. Does this cause the ports to be undetected?

But if i use Diva, the ports are detected correctly. Please advise.
 

PaloAlto

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there should normally be a layer called M1.pn instead of M1.dw

You should use the .pn one
 

fixrouter4400

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It depends on the process technology...
some process used the same PIN and Port layers ...e.g M1 pin to Mn pin where n is any number of metal layers...but some process used PIN layer for the pin and Port layer for the text. e.g M1 pin / M1 pt.

Added after 3 minutes:

crystal said:
The pin layers are in drawing layers. Does this cause the ports to be undetected?

But if i use Diva, the ports are detected correctly. Please advise.
Calibre is case and layer sensitive...you must used the metal pin not the metal drawing layer M1 dg...if it's in metal 1 used the M1 pin layer and M1 pin text.
 

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