moonnightingale
Full Member level 6
Hi
I have written a code.
Can some body just see the code and confirm me that it is ok
The Circuit diagram is also attached for which code is written.
module logiccircuit(A,B,Y,YY,X,XX,clock);
output reg A,B,Y,YY;
input X,XX,clock;
reg E,F;
always@(posedge clock)
begin
E=((A&~X)|(A&~B)|(~A&B&X));
F=(B^X);
A<=E;
B<=F;
Y<=A;
YY<=B;
end
endmodule
I have written a code.
Can some body just see the code and confirm me that it is ok
The Circuit diagram is also attached for which code is written.
module logiccircuit(A,B,Y,YY,X,XX,clock);
output reg A,B,Y,YY;
input X,XX,clock;
reg E,F;
always@(posedge clock)
begin
E=((A&~X)|(A&~B)|(~A&B&X));
F=(B^X);
A<=E;
B<=F;
Y<=A;
YY<=B;
end
endmodule