Pls help on layout extraction

[dshuang001]

Hello

I got error messages when do extraction before LVS in IC5141:
error: Layer POLY is the common serial number source for connect layers:
POLY cap_poly cap_p12_term2.
info: If short location check is desired later on, check the saveInterconnect
statement for correctness:
Interconnect layer ptapc, pad_NPdio, ...... not saved.
And it concludes there are errors in the extract technology file.

But when i run it in IC44XX version use the same technology file, no problem occurs.

Please help me on it, thanks.

 

[cougar168]

are you using dracula or assura?

 

[dshuang001]

Sorry, I am using diva.

I am not sure if it is due to the difference between IC5141 and IC 44XX.