hmm, things are not that easy my friend, and changing the width is not the only parameter here. You say you are now focused on the leakage power, but if we also do not consider the elimination of power-related failures by addressing voltage-drop and EM, there is another effect that contributes to the total power dissipation; dynamic power. You should probably know these concepts, but just in case, dynamic power occurs when a transistor switches state and is due to capacitive charging and discharging whereas leakage power arises due to leakage current flowing through the transistor.
Since you are now focussed on the leakage effect, lets go with it. Here are the bad news
leakage current can even consume power in standby or sleep modes of operation. Besides, with each step down in process geometry, leakage power has more or less doubled in magnitude, namely for 90nm process technology, leakage power contributes 40 to 50 percent of the total power budget, with active power dissipation from transistor switching making up the rest.
you are now saying that you will increase the width for the sake of decrease in leakage effects, but once the width is increased, the device thresholds also increase. You will be needing higher supply voltage requirements, and that will lead an increase in the dynamic power dissipation!
Well, actaully what i am saying it, rather than focusing on the width and stuff, look at the big picture, look at the system as a whole. there are some trade-offs to consider here.