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In synchronous dual port SRAM, clocka(portA) and clockb(portB) can be different ( in frequency or phase).
but the problem is when portA and portB access to 1 location( and violate the timing of RAM), the data in that location may be corrupted
---> you need a control method between clocka and clockb
+ clocka and clockb is different in frequency but have a fixed-phase-relationship(divided clocks) ---> satisfy timing between portA/portB access at same location
+ clocka and clockb is different in frequency and phase ----> need a control method to avoid same address access.