please help understand the ucf code snippet

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syedshan

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hi all,

please see the following snippet.

Code:
#INST "*/i_clkrst_*/bufg_slow_capt" LOC = BUFGCTRL_X0Y26;
INST "*/i_clkrst_*/i_ddr_pll/clkout5_buf" LOC = BUFGCTRL_X0Y27;
INST "*/i_clkrst_*/bufg_fast_capt" LOC = BUFGCTRL_X0Y28;
INST "*/i_clkrst_*/i_ddr_pll/clkout1_buf" LOC = BUFGCTRL_X0Y29;
INST "*/i_clkrst_*/clk_200_inst/clkout1_buf" LOC = BUFGCTRL_X0Y4;
INST "*/i_clkrst_*/bufg_capt_reset" LOC = BUFGCTRL_X0Y5;
INST "*/i_clkrst_*/i_ddr_pll/mmcm_adv_inst" LOC = MMCM_ADV_X0Y11;

I want to know what it actually does, does it mean the following

1. INST will call the respective internal clock signals and then connect them to BUFGCTRL, but what will it achieve. Also why the Slice dimensions are necessary here?

thanks
 


it just says which resource in location x y will be used for this function. this is not SCLICE location, but resource xy locaions.
i guess you can see it in fpga editor - floor planner
 

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